A Novel Hybrid Filter-Based PLL to Eliminate Effect of Input Harmonics and DC Offset

Synchronous reference frame phase locked loop (SRF-PLL) is widely used for grid synchronization and control in grid-connected applications. A major problem with SRF-PLL is how to improve its dynamic performance and filtering capability under complex grid conditions such as unbalance, distortion, and dc offset mixing without affecting its phase tracking performance and stability. In order to achieve this goal, a novel second-order generalized integrator (NSOGI) and a modified NSOGI (MNSOGI) with dc offset rejection capability based on NSOGI are proposed, and then, an effective hybrid filter is designed and incorporated into the inner loop of a SRF-PLL. The proposed hybrid filter is a combination of a dual MNSOGI and a moving average filter (MAF), it can block the fundamental frequency negative sequence component, dc offset component, and the rest of harmonic components in the SRF-PLL input three-phase voltages at the same time with a simple complexity. The proposed PLL in this paper has a faster transient response due to reducing the window length of the MAF. A small-signal model of the proposed PLL is derived. The stability is analyzed, and parameters design guidelines are given. The effectiveness of the proposed PLL is confirmed through simulation experimental results.