The Evolution of Channelization Receiver Architecture: Principles and Design Challenges

This paper presents a broadband receiver architecture with series and parallel channelization. The proposed architecture decomposes the broadband incident spectrum into multiple channels, and achieves fast switching time, while using the single synthesizer with a fixed local oscillator (LO) frequency. Channelized receiver is a good candidate for critical RF processing tasks, such as data conversion, broadband radio, and spectrum analysis. The key feature of the proposed channelized receiver is the decomposition of the broadband frequency spectrum through parallel band partition and series channel selection. Relevant design challenges of the channelization receiver are discussed. In addition, the radio impairments determining the key performance of the radio are analyzed. The prototype receiver front-end was designed and implemented in 45 nm CMOS technology to demonstrate the effectiveness of the proposed architecture. The receiver front-end prototype splits an input spectrum of dc-40 GHz into four sub-bands with 10 GHz IF bandwidth and dissipates the average power of 33 mA and 60 mA from RF and LO blocks, respectively, while achieving <;5 dB NF and <;-145 dBc/Hz phase noise.