Comprehensive Analysis of Gate-Induced Drain Leakage in Emerging FET Architectures: Nanotube FETs Versus Nanowire FETs

In this paper, we have performed a comprehensive analysis of the gate-induced drain leakage (GIDL) in emerging nanotube (NT) and nanowire (NW) FET architectures. We demonstrate that the additional lateral band-to-band-tunneling (L-BTBT) in the NTFETs owing to the core gate increases their OFF-state current compared with the NWFETs. The increased L-BTBT results in a significantly degraded performance of NTFETs when the gate lengths are scaled to the sub-10-nm regime. Therefore, the enhanced gate control offered by the NT architecture is detrimental from L-BTBT GIDL perspective. We show that although the core gate leads to a considerable increase in the gate capacitance of NTFETs, their dynamic performance improves compared with NWFETs due to the enhanced effective drive current owing to the NT architecture. In addition, we also provide the necessary design guidelines for the NTFETs and NWFETs with respect to spacer dielectric constant, intrinsic material bandgap, effective oxide thickness, supply voltage, and NT diameter from L-BTBT GIDL perspective.