Design of Low-Power Multiplierless Linear-Phase FIR Filters

In the design of multiplierless finite impulse response (FIR) filters, tremendous efforts have been made to reduce the number of adders of the multiplier block for the reduction of overall chip area and power consumption. However, fewer in the multiplier block do not necessarily lead to lower power consumption, since the structural adders dominate the power consumption of an FIR filter circuit. In this paper, we propose a power-oriented optimization method for linear phase FIR filters. In the proposed algorithm, the power index, which is the average adder depth of the structural adders, is used as the optimization objective in the discrete coefficients search. A gate-level simulation of benchmark filters shows that the proposed technique designs filters consuming less power than those obtained by the best available algorithms, which aim to minimize the number of adders. The power savings over existing designs can be as much as 19.6%.