Open AccessDigital-to-Time Converter with 3.93 ps Resolution Implemented on FPGA Chips
Author(s) -
Min Zhang,
Hai Wang,
Yan Liu
Publication year - 2017
Publication title -
ieee access
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.587
H-Index - 127
ISSN - 2169-3536
DOI - 10.1109/access.2017.2700055
Subject(s) - aerospace , bioengineering , communication, networking and broadcast technologies , components, circuits, devices and systems , computing and processing , engineered materials, dielectrics and plasmas , engineering profession , fields, waves and electromagnetics , general topics for engineers , geoscience , nuclear engineering , photonics and electrooptics , power, energy and industry applications , robotics and control systems , signal processing and analysis , transportation
In this paper, a digital-to-time converter (DTC) based on the principle of quantified phase shift resolution (QPSR) is proposed and tested. The QPSR principle is realized by analyzing the phase relationship between two periodic signals, which distinguishes the proposed DTC from conventional DTCs. For performance evaluation, the proposed DTC is implemented on Xilinx Virtex-5 and Virtex-6 field programmable gate array (FPGA) chip, respectively. The obtained resolution of the DTC implemented on Virtex-5 FPGA is 27.1 ps, and the differential nonlinearity (DNL) and integral nonlinearity (INL) are -0.269~+0.247 least significant bit (LSB) and -0.387~+0.171 LSB. Meanwhile, the DTC implemented on Virtex-6 FPGA can achieve a resolution of 3.93 ps, a dynamic range of 43 s, a DNL of -0.327~+0.358 LSB, and an INL of -2.6093~+2.4754 LSB. Experimental results prove that the proposed DTC features high-accuracy, low-cost, and easy implementation.
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