A New Parallel Sorting Algorithm and its Efficient VLSI Implementation | Zendy

S. Dey | Zendy; Pradip K. Srimani | Zendy

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A New Parallel Sorting Algorithm and its Efficient VLSI Implementation

Author(s) -

S. Dey,

Pradip K. Srimani

Publication year - 1990

Publication title -

the computer journal

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 0.319

H-Index - 64

eISSN - 1460-2067

pISSN - 0010-4620

DOI - 10.1093/comjnl/33.3.241

Subject(s) - computer science , simd , parallel computing , sorting , very large scale integration , sorting algorithm , parallel algorithm , time complexity , algorithm , binary logarithm , embedded system , mathematics , combinatorics

We develop a new parallel algorithm for sorting which has a time complexity of O(log n) and requires n 2 /log n processors. The algorithm can be readily mapped on an SIMD mesh connected array of processors which has all the features of efficient VLSI implementation. The corresponding hardware algorithm maintains the O(log n) execution time and has a low O(n) interprocessor communication time

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