Generating Permutations on a VLSI Suitable Linear Network | Zendy

Michel Cosnard | Zendy; A.G. Ferreira | Zendy

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Generating Permutations on a VLSI Suitable Linear Network

Author(s) -

Michel Cosnard,

A.G. Ferreira

Publication year - 1989

Publication title -

the computer journal

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 0.319

H-Index - 64

eISSN - 1460-2067

pISSN - 0010-4620

DOI - 10.1093/comjnl/32.6.571

Subject(s) - permutation (music) , very large scale integration , computer science , parallel computing , combinatorics , sequence (biology) , position (finance) , mathematics , algorithm , embedded system , physics , finance , biology , acoustics , economics , genetics

A parallel algorithm for generating all the k! permutations of k P k for every (1≤k≤n) is presented. The architecture consists of a linear processor array with n elements. The network is VLSI implementable and fault tolerant. With a simple modification in the algorithm performed by the processors, the network is able to generate combinations

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