Welcome and Opening Remarks

Proposal of system platform model a semiconductor business model in the age of digital consumer products Silicon technology emerging trends from a system application perspective Fermi level pinning at the polySi/metal oxide interface The breakthrough in data retention time of DRAM using recess-channel-array transistor(RCAT) for 88nm feature size and beyond Highly stable 65nm node (CMOS5) 0.56[mu]m[superscript 2] SRAM cell design for very low operation voltage A 0.18[mu]m logic-based MRAM technology for high performance nonvolatile memory applications Fabrication of HfSiON gate dielectrics by plasma oxidation and nitridation, optimized for 65nm node low power CMOS applications Design guideline of HfSiON gate dielectric for 65 nm CMOS generation Comparison of sub 1 nm TiN/HfO[subscript 2] with poly-Si/HfO[subscript 2] gate stacks using scaled chemical oxide interfaces Novel plasma enhanced atomic layer deposition technology for high-k capacitor with EOT of 8A on conventional metal electrode Design and proof of high quality HfAlO[subscript x] film formation for MOSCAPs and nMOSFETs through layer-by-layer deposition and annealing process Novel multi-bit SONOS type flash memory using a high-k charge trapping layer 3D TFT-SONOS memory cell for ultra-high density file storage applications Highly manufacturable SONOS non-volatile memory for the embedded SoC solution Theoretical and experimental investigation of Si nanocrystal memory device with HfO[subscript 2] high-k tunneling dielectric Silicon nitride trap memory with double tunnel junction The impact of oxynitride process, deuterium annealing and STI stress to 1/f noise of 0.11 [mu]m CMOS Low-K/Cu CMOS logic based SoC technology for 10Gb transceiver with 115GHzf[subscript T], 80GHz f[subscript MAX] RF CMOS, high-Q MiM capacitor and spiral Cu inductor