Open AccessVLSI Implementation Of High Speed Low Power Design Using Hybrid Power Gating Technique
Author(s) -
S. Pousia,
K. Murugan
Publication year - 2021
Publication title -
iop conference series. materials science and engineering
Language(s) - English
Resource type - Journals
eISSN - 1757-899X
pISSN - 1757-8981
DOI - 10.1088/1757-899x/1084/1/012058
Subject(s) - xnor gate , power gating , leakage power , cmos , transistor , leakage (economics) , electronic engineering , computer science , adder , power (physics) , transmission gate , electrical engineering , engineering , voltage , physics , quantum mechanics , economics , macroeconomics
Nowadays, low powerhigh speed CMOS design is one among the challenging issues. As the technology is scaling down, the static power consumption has turned into a remarkableconcern. The proposed methodology incorporates the following technique such as sleep technique, stack technique, sleepy stack technique, sleepy keeper technique, leakage control transistor technique (LECTOR) and sleepy keeper leakage control transistor technique (SK-LCT) for leakage power reduction. The proposed power gating techniquelead to low power,high speed CMOS design. The xor gate, xnor gate, half adder & 6T sram cell is outlined using newly proposed power gating technique for a low power high speed design.When compared to the conventional methodology xor gate saves 19.95 % of power & 33.75% of delay, xnor gate saves 12 % of power & 23.29 % of delay, half adder saves 35.29% of power &25.69% of delay and sram cell saves 14.29% of power & 34.37 % of delay. Simulation is done using Tanner EDA tool and the outcomes demonstrate a noteworthy change in leakage power utilization and speed.