Open AccessResearch on Low Power Design Technology of HPLC
Author(s) -
Chunliang Zhou,
Yan Hao,
Xiaohui Zhang,
Zheng Li,
Xiaoke Tang
Publication year - 2021
Publication title -
journal of physics. conference series
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.21
H-Index - 85
eISSN - 1742-6596
pISSN - 1742-6588
DOI - 10.1088/1742-6596/1920/1/012050
Subject(s) - computer science , power line communication , chip , context (archaeology) , embedded system , power (physics) , telecommunications , paleontology , physics , quantum mechanics , biology
Power line communication (PLC) is widely used in electric power Internet of Things (IoT). Its performance, including data rate and anti-interference ability, has made great breakthroughs from Narrowband PLC (NB PLC) to high-speed PLC (HPLC) in recent years. In the context of continuously improving functions, the power consumption of HPLC is gradually increasing, this is equivalent to increasing the line loss of power transmission, which has an adverse effect on the large-scale deployment of HPLC. This paper analyses the structure of HPLC chip and communication unit, mainly exploring the low power design technology from chip architecture design, frequency band selection, physical layer (PHY) design, and MAC layer process. Currently the latest HPLC chip has been developed successfully, and the corresponding communication unit have started large-scale applications, and lab test and field application results show the HPLC can well meet the power consumption requirements in electric power IoT.