Channel geometry-dependent threshold voltage and transconductance degradation in gate-all-around nanosheet junctionless transistors
Author(s) -
DaeYoung Jeon
Publication year - 2021
Publication title -
aip advances
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.421
H-Index - 58
ISSN - 2158-3226
DOI - 10.1063/5.0035460
Subject(s) - transconductance , nanosheet , materials science , threshold voltage , transistor , degradation (telecommunications) , cmos , optoelectronics , logic gate , scaling , voltage , channel (broadcasting) , nanotechnology , electrical engineering , geometry , engineering , mathematics
Accelerating Research
Robert Robinson Avenue,
Oxford Science Park, Oxford
OX4 4GP, United Kingdom
Address
John Eccles HouseRobert Robinson Avenue,
Oxford Science Park, Oxford
OX4 4GP, United Kingdom