Open AccessFirst level interconnection based on optimization of Cu stud bump for chip to chip package
Author(s) -
M. R. Lim,
Zaliman Sauli,
H. Aris,
Vithyacharan Retnasamy,
Jeffery C. C. Lo,
K. Muniandy,
Navas Khan,
Chee S. Foong
Publication year - 2018
Publication title -
aip conference proceedings
Language(s) - English
Resource type - Conference proceedings
eISSN - 1551-7616
pISSN - 0094-243X
DOI - 10.1063/1.5080908
Subject(s) - flip chip , interconnection , chip , materials science , wire bonding , chip scale package , thermal copper pillar bump , soldering , die (integrated circuit) , three dimensional integrated circuit , integrated circuit , structural engineering , composite material , electrical engineering , computer science , optoelectronics , engineering , nanotechnology , layer (electronics) , computer network , adhesive
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