Open Access16×16 fast signed multiplier using Booth and Vedic architecture
Author(s) -
L. Z. Shing,
Razaidi Hussin,
Afzan Kamarudin,
S. N. Mohyar,
S. Taking,
M. H. A. Aziz,
N. Ahmad
Publication year - 2018
Publication title -
aip conference proceedings
Language(s) - English
Resource type - Conference proceedings
eISSN - 1551-7616
pISSN - 0094-243X
DOI - 10.1063/1.5080898
Subject(s) - multiplier (economics) , booth's multiplication algorithm , adder , arithmetic , mathematics , architecture , computer science , computer hardware , telecommunications , economics , macroeconomics , latency (audio) , art , visual arts
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