Nanoscale patterning of electronic devices at the amorphous LaAlO3/SrTiO3 oxide interface using an electron sensitive polymer mask

A simple approach is presented for designing complex oxide mesoscopic electronic devices based on the conducting interfaces of room temperature grown LaAlO3/SrTiO3 heterostructures. The technique is based entirely on methods known from conventional semiconductor processing technology, and we demonstrate a lateral resolution of ∼100 nm. We study the low temperature transport properties of nanoscale wires and demonstrate the feasibility of the technique for defining in-plane gates allowing local control of the electrostatic environment in mesoscopic devices.A simple approach is presented for designing complex oxide mesoscopic electronic devices based on the conducting interfaces of room temperature grown LaAlO3/SrTiO3 heterostructures. The technique is based entirely on methods known from conventional semiconductor processing technology, and we demonstrate a lateral resolution of ∼100 nm. We study the low temperature transport properties of nanoscale wires and demonstrate the feasibility of the technique for defining in-plane gates allowing local control of the electrostatic environment in mesoscopic devices.