Control of O-H bonds at a-IGZO/SiO2 interface by long time thermal annealing for highly stable oxide TFT
Author(s) -
Jae Kwon Jeon,
Jae Gwang Um,
Suhui Lee,
Jin Jang
Publication year - 2017
Publication title -
aip advances
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.421
H-Index - 58
ISSN - 2158-3226
DOI - 10.1063/1.5008435
Subject(s) - annealing (glass) , thin film transistor , materials science , x ray photoelectron spectroscopy , amorphous solid , threshold voltage , optoelectronics , transistor , analytical chemistry (journal) , crystallography , voltage , nanotechnology , chemistry , chemical engineering , metallurgy , electrical engineering , layer (electronics) , chromatography , engineering
We report two-step annealing, high temperature and sequent low temperature, for amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistor (TFT) to improve its stability and device performance. The annealing is carried out at 300 oC in N2 ambient for 1 h (1st step annealing) and then at 250 oC in vacuum for 10 h (2nd step annealing). It is found that the threshold voltage (VTH) changes from 0.4 V to -2.0 V by the 1st step annealing and to +0.6 V by 2nd step annealing. The mobility changes from 18 cm2V-1s-1 to 25 cm2V-1s-1 by 1st step and decreases to 20 cm2V-1s-1 by 2nd step annealing. The VTH shift by positive bias temperature stress (PBTS) is 3.7 V for the as-prepared TFT, and 1.7 V for the 1st step annealed TFT, and 1.3 V for the 2nd step annealed TFT. The XPS (X-ray photoelectron spectroscopy) depth analysis indicates that the reduction in O-H bonds at the top interface (SiO2/a-IGZO) by 2nd step annealing appears, which is related to the positive VTH shift and smaller VTH shift by PBTS
Accelerating Research
Robert Robinson Avenue,
Oxford Science Park, Oxford
OX4 4GP, United Kingdom
Address
John Eccles HouseRobert Robinson Avenue,
Oxford Science Park, Oxford
OX4 4GP, United Kingdom