Open AccessA 2x2 bit Vedic multiplier with different adders in 90nm CMOS technology
Author(s) -
Lee Shing Jie,
Siti Hawa Ruslan
Publication year - 2017
Publication title -
aip conference proceedings
Language(s) - English
Resource type - Conference proceedings
SCImago Journal Rank - 0.177
H-Index - 75
eISSN - 1551-7616
pISSN - 0094-243X
DOI - 10.1063/1.5002035
Subject(s) - adder , multiplier (economics) , xor gate , cmos , arithmetic , transistor , transistor count , electronic circuit , computer science , serial binary adder , multiplication (music) , 4 bit , logic gate , voltage , power consumption , electronic engineering , mathematics , power (physics) , electrical engineering , algorithm , engineering , physics , combinatorics , economics , macroeconomics , quantum mechanics
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