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Fully tensile strained partial silicon-on-insulator n-type lateral-double-diffused metal-oxide-semiconductor field effect transistor using localized contact etching stop layers
Author(s) -
Xiangzhan Wang,
Changgui Tan,
Xi Zou,
Yi Zhang,
J. Pan,
Yang Liu
Publication year - 2017
Publication title -
aip advances
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.421
H-Index - 58
ISSN - 2158-3226
DOI - 10.1063/1.4983214
Subject(s) - ldmos , materials science , optoelectronics , transistor , etching (microfabrication) , silicon , contact resistance , field effect transistor , silicon on insulator , breakdown voltage , stress (linguistics) , layer (electronics) , electrical engineering , voltage , composite material , linguistics , philosophy , engineering
The use of contact etching stop layer (CESL) stressors is a popular technique forintroducing stress into a transistor channel. However, when tensile stress is applied to ann-type lateral double-diffused metal-oxide-semiconductor (LDMOS) by covering the whole device with a CESL, the driftregion adjacent to the channel will be compressively strained, which is detrimental todeviceperformance. The current work presents a strained partial silicon-on-insulator LDMOS inwhich tensile stress was introduced in both the channel and drift region via a CESL toreduce the device’s on-resistance and improve its frequency performance. An n-type LDMOSdevice with atop-layer Si thickness that was varied between 300 and 20 nm was simulated to investigatethe effect of CESLs on device performance. Devices in which the channel and drift region were fullystrained had larger carrier mobilities, and their cut-off frequencies were increased by25% compared with a normal unstrained partial silicon-on-insulator LDMOS field effecttransistor. Meanwhile stress was shown to have little impact on the breakdown voltage ofthe two types of LDMOS field effect transistor studied here

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