Open AccessA SONOS device with a separated charge trapping layer for improvement of charge injection
Author(s) -
Jae-Hyuk Ahn,
Dong-Il Moon,
Seung-Won Ko,
ChangHoon Kim,
Jee Yeon Kim,
Moon-Seok Kim,
MyeongLok Seol,
Joon-Bae Moon,
JiMin Choi,
Jae-Sub Oh,
SungJin Choi,
YangKyu Choi
Publication year - 2017
Publication title -
aip advances
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.421
H-Index - 58
ISSN - 2158-3226
DOI - 10.1063/1.4978322
Subject(s) - materials science , trapping , flash memory , optoelectronics , charge (physics) , dielectric , threshold voltage , flash (photography) , non volatile memory , gate dielectric , layer (electronics) , charge trap flash , voltage , hot carrier injection , oxide , gate oxide , channel (broadcasting) , electrical engineering , transistor , nanotechnology , computer science , optics , physics , nand gate , engineering , ecology , quantum mechanics , metallurgy , biology , operating system
A charge trapping layer that is separated from the primary gate dielectric is implemented on a FinFET SONOS structure. By virtue of the reduced effective oxide thickness of the primary gate dielectric, a strong gate-to-channel coupling is obtained and thus short-channel effects in the proposed device are effectively suppressed. Moreover, a high program/erase speed and a large shift in the threshold voltage are achieved due to the improved charge injection by the reduced effective oxide thickness. The proposed structure has potential for use in high speed flash memory
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