Improved electrical properties of atomic layer deposited tin disulfide at low temperatures using ZrO2 layer | Zendy

Juhyun Lee | Zendy; Jeongsu Lee | Zendy; Giyul Ham | Zendy; Seokyoon Shin | Zendy; Joo Hyun Park | Zendy; Hyeongsu Choi | Zendy; Seungjin Lee | Zendy; JuYoung Kim | Zendy; Onejae Sul | Zendy; SeungBeck Lee | Zendy; Hyeongtag Jeon | Zendy

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Improved electrical properties of atomic layer deposited tin disulfide at low temperatures using ZrO₂ layer

Author(s) -

Juhyun Lee,

Jeongsu Lee,

Giyul Ham,

Seokyoon Shin,

Joo Hyun Park,

Hyeongsu Choi,

Seungjin Lee,

JuYoung Kim,

Onejae Sul,

SeungBeck Lee,

Hyeongtag Jeon

Publication year - 2017

Publication title -

aip advances

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 0.421

H-Index - 58

ISSN - 2158-3226

DOI - 10.1063/1.4977887

Subject(s) - materials science , raman spectroscopy , atomic layer deposition , high resolution transmission electron microscopy , annealing (glass) , passivation , tin , optoelectronics , electron mobility , chemical vapor deposition , field effect transistor , transmission electron microscopy , nanotechnology , layer (electronics) , transistor , composite material , metallurgy , optics , electrical engineering , physics , engineering , voltage

We report the effect of zirconium oxide (ZrO2) layers on the electrical characteristics of multilayered tin disulfide (SnS2) formed by atomic layer deposition (ALD) at low temperatures. SnS2 is a two-dimensional (2D) layered material which exhibits a promising electrical characteristics as a channel material for field-effect transistors (FETs) because of its high mobility, good on/off ratio and low temperature processability. In order to apply these 2D materials to large-scale and flexible electronics, it is essential to develop processes that are compatible with current electronic device manufacturing technology which should be conducted at low temperatures. Here, we deposited a crystalline SnS2 at 150 °C using ALD, and we then annealed at 300 °C. X-ray diffraction (XRD) and Raman spectroscopy measurements before and after the annealing showed that SnS2 had a hexagonal (001) peak at 14.9° and A1g mode at 313 cm−1. The annealed SnS2 exhibited clearly a layered structure confirmed by the high resolution transmission electron microscope (HRTEM) images. Back-gate FETs with SnS2 channel sandwiched by top and bottom ZrO2 on p++Si/SiO2 substrate were suggested to improve electrical characteristics. We used a bottom ZrO2 layer to increase adhesion between the channel and the substrate and a top ZrO2 layer to improve contact property, passivate surface, and protect from process-induced damages to the channel. ZTZ (ZrO2/SnS2/ZrO2) FETs showed improved electrical characteristics with an on/off ratio of from 0.39×103 to 6.39×103 and a mobility of from 0.0076 cm2/Vs to 0.06 cm2/Vs

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