Local mapping of interface traps using contactless capacitance transient technique | Zendy

Haruhiko Yoshida | Zendy; Hidenobu Mori | Zendy

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Local mapping of interface traps using contactless capacitance transient technique

Author(s) -

Haruhiko Yoshida,

Hidenobu Mori

Publication year - 2016

Publication title -

aip advances

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 0.421

H-Index - 58

ISSN - 2158-3226

DOI - 10.1063/1.4964700

Subject(s) - capacitance , transient (computer programming) , wafer , optoelectronics , materials science , electrostatic discharge , differential capacitance , semiconductor , interface (matter) , deep level transient spectroscopy , parasitic capacitance , capacitive sensing , electrical engineering , silicon , voltage , electrode , chemistry , computer science , engineering , composite material , capillary number , capillary action , operating system

Contactless capacitance transient techniques have been applied to local mapping of interface traps of a semiconductor wafer. In contactless capacitance transient techniques, a Metal-Air gap-Oxide-Semiconductor (MAOS) structure is used instead of a conventional Metal-Oxide-Semiconductor (MOS) structure. The local mapping of interface traps was obtained by using a contactless Isothermal Capacitance Transient Spectroscopy (ICTS), which is one of the contactless capacitance transient techniques. The validity of the contactless ICTS was demonstrated by characterizing a partially Au-doped Si wafer. The results revealed that local mapping of interface traps using contactless capacitance transient techniques is effective in wafer inspection and is a promising technique for the development of MOS devices and solar cells with high reliability and high performance

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