New Products

Edge Computer has announced the Edge 1000 family of superminicom-puters, targeted at value-added resellers and systems integrators using the Moto-rola 68010/20 microprocessors. According to the company, the new processors are 32-bit superminicom-puters implementing the Motorola instruction set in the Edge mainframe architecture. This reportedly delivers RISC-like performance through Moto-rola's CISC-based 68000 family instruction set. The dual-processor Edge 1200 with 8M bytes of system memory, 337M bytes of hard disk storage, and the GSX Unix operating system costs around $128,000. It reputedly achieves 11 million instructions per second. The single-processor Edge 1100 in the same configuration costs $104,000. It reputedly achieves 6 MIPS. The 1000 family reputedly features an average instruction time of 1.59 cycles per instruction, with memory boards using dual surface mount technology for high density. The 32-bit processor is a VLSI implementation of a Harvard supercomputer architecture that simultaneously fetches instructions and operands over multiple 32-bit buses. The dual four-state pipelined processor overlaps the execution of multiple instructions. The CPU has two independent, decoupled pipelines: the instruction fetch pipeline and the operand executive pipeline. IFP fetches instructions and OEP decodes and executes them. Pipeline performance relies on the branch prediction unit, which consists of a 4096-entry branch cache and a 16-entry last-in/first-out return stack. The floating-point accelerator conforms to the IEEE standard 754, draft 10.0, and supports 32-bit and 64-bit floating-point formats and 8-, 16-, and 32-bit signed and unsigned integer formats. Both the Edge 1100 single-processor and the Edge 1200 dual-processor models fit into a 17-inch wide, 29-inch high cabinet that includes peripherals and up to 64M bytes of memory.