Scaling limit of digital circuits due to thermal noise

The error probability at a node of a digital circuit exposed to thermal noise agitation is investigated and the minimal dissipation–reliability relation for practical electronic circuits is derived. The digital circuit is modeled by an inverter chain with ideal transfer characteristics, and the error probability due to spurious data transfer caused by the thermal noise fluctuation is evaluated as a function of the node switching energy. The maximal error probability at each node allowed by the reliability requirement of the total system leads us to the minimal node energy dissipated per logical switching, which amounts to around 12 eV in the future 1010 gate system operated at a 10 GHz clock rate with a 104 FIT level reliability. In view of the device size-scaling trend of large-scale integrated circuits, the minimal node energy is expected to be reached at a feature size of 10–20 nm