Open AccessElectrical characteristics of asymmetrical silicon nanowire field-effect transistors
Author(s) -
Soshi Sato,
Kuniyuki Kakushima,
Kenji Ohmori,
Kenji Natori,
Keisaku Yamada,
Hiroshi Iwai
Publication year - 2011
Publication title -
applied physics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 1.182
H-Index - 442
eISSN - 1077-3118
pISSN - 0003-6951
DOI - 10.1063/1.3665261
Subject(s) - materials science , nanowire , silicon , electric field , field effect transistor , optoelectronics , enhanced data rates for gsm evolution , drain induced barrier lowering , transistor , surface roughness , electron mobility , silicon nanowires , condensed matter physics , nanotechnology , composite material , voltage , electrical engineering , physics , engineering , telecommunications , quantum mechanics , computer science
This letter reports the electrical characteristics of nonuniform silicon nanowire nFETs with asymmetric source and drain widths. For electrostatic properties, reduced drain-induced barrier lowering (DIBL) is achieved in a device in which the source is wider than the drain. For carrier transport properties, higher values of surface-roughness-limited mobility (μSR) are obtained in the sample with the wider drain size. Our electrostatic model shows that the concentration of lines of electric force is relaxed near the wider source edge, which results in smaller DIBL. The asymmetric μSR is attributed to the channel surface morphology with (110)- and (100)-faceted surfaces
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