Open AccessGate-bias stress in amorphous oxide semiconductors thin-film transistors
Author(s) -
M. E. Lopes,
Henrique L. Gomes,
M. C. R. Medeiros,
Pedro Barquinha,
L. Pereira,
Elvira Fortunato,
Rodrigo Martins,
I. Ferreira
Publication year - 2009
Publication title -
applied physics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 1.182
H-Index - 442
eISSN - 1077-3118
pISSN - 0003-6951
DOI - 10.1063/1.3187532
Subject(s) - thin film transistor , materials science , threshold voltage , amorphous solid , optoelectronics , transistor , amorphous silicon , relaxation (psychology) , dielectric , gate oxide , silicon , gate dielectric , voltage , nanotechnology , chemistry , crystalline silicon , crystallography , electrical engineering , layer (electronics) , psychology , social psychology , engineering
A quantitative study of the dynamics of threshold-voltage shifts with time in gallium-indium zinc oxide amorphous thin-film transistors is presented using standard analysis based on the stretched exponential relaxation. For devices using thermal silicon oxide as gate dielectric, the relaxation time is 3 105 s at room temperature with activation energy of 0.68 eV. These transistors approach the stability of the amorphous silicon transistors. The threshold voltage shift is faster after water vapor exposure suggesting that the origin of this instability is charge trapping at residual-water-related trap sites
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