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The authors report studies of the effect of grain alignment on interface trap density of thermally oxidized aligned-crystalline silicon (ACSi) films by means of capacitance-voltage (C-V) measurements. C-V curves were measured on metal-oxide-semiconductor (MOS) capacitors fabricated on ⟨001⟩-oriented ACSi films on polycrystalline substrates. From high-frequency C-V curves, the authors calculated a decrease of interface trap density from 2×1012to1×1011cm−2eV−1 as the grain mosaic spread in ACSi films improved from 13.7° to 6.5°. These results demonstrate the effectiveness of grain alignment as a process technique to achieve significantly enhanced performance in small-grained (⩽1μm) polycrystalline Si MOS-type devices.

Effect of grain alignment on interface trap density of thermally oxidized aligned-crystalline silicon films