Modeling of high-current source-gated transistors in amorphous silicon | Zendy

Frantisek Balon | Zendy; J. M. Shan | Zendy; B.J. Sealy | Zendy

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Modeling of high-current source-gated transistors in amorphous silicon

Author(s) -

Frantisek Balon,

J. M. Shan,

B.J. Sealy

Publication year - 2005

Publication title -

applied physics letters

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 1.182

H-Index - 442

eISSN - 1077-3118

pISSN - 0003-6951

DOI - 10.1063/1.1865348

Subject(s) - transistor , materials science , output impedance , silicon , optoelectronics , field effect transistor , current source , amorphous silicon , amorphous solid , voltage , current (fluid) , saturation (graph theory) , electrical impedance , voltage source , thin film transistor , electrical engineering , nanotechnology , engineering , chemistry , crystalline silicon , crystallography , mathematics , combinatorics , layer (electronics)

Compared with the field-effect transistor, the source-gated transistor has a much lower saturation voltage and higher output impedance. These features are investigated using computer modeling for amorphous silicon transistors operated at high currents when source barriers are low. In particular, it is shown that low saturation voltages are maintained at high current and are insensitive to source-drain separation. Furthermore, the output impedance is preserved even for submicron source-drain separations.

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