In-line, Non-destructive Electrical Metrology of Nitrided Silicon Dioxide and High-k Gate Dielectric Layers | Zendy

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In-line, Non-destructive Electrical Metrology of Nitrided Silicon Dioxide and High-k Gate Dielectric Layers

Author(s) -

Robert Hillard

Publication year - 2003

Publication title -

aip conference proceedings

Language(s) - English

Resource type - Conference proceedings

SCImago Journal Rank - 0.177

H-Index - 75

eISSN - 1551-7616

pISSN - 0094-243X

DOI - 10.1063/1.1622560

Subject(s) - materials science , dielectric , gate dielectric , optoelectronics , capacitance , metrology , high κ dielectric , voltage , conductance , electrical engineering , electrode , transistor , optics , condensed matter physics , chemistry , physics , engineering

Highly sensitive, accurate and precise methods for measuring the properties of dielectrics used in sub 0.13 μm technology are required. It is particularly critical to monitor the electrical properties of the gate dielectric. The electrical properties of thin dielectrics are assessed with a new, non‐contaminating, non‐damaging elastic probe. This probe forms a small diameter (∼30 μm to 50 μm ) Elastic Metal gate (EM‐gate) on the surface of a dielectric. Subsequent electrical measurements are made with advanced Capacitance‐Voltage (CV), Conductance‐Voltage (GV), and Current‐Voltage (IV) techniques. Valuable and essential information about the dielectric thickness and quality, leakage current, Si‐SiO2 interface quality, and channel carrier density profile is obtained.

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