Soft-breakdown-suppressed ultrathin atomic-layer-deposited silicon–nitride/SiO2 stack gate dielectrics for advanced complementary metal–oxide–semiconductor technology | Zendy

Quazi D. M. Khosru | Zendy; Anri Nakajima | Zendy; Takashi Yoshimoto | Zendy; Shin Yokoyama | Zendy

Open Access

Soft-breakdown-suppressed ultrathin atomic-layer-deposited silicon–nitride/SiO2 stack gate dielectrics for advanced complementary metal–oxide–semiconductor technology

Author(s) -

Quazi D. M. Khosru,

Anri Nakajima,

Takashi Yoshimoto,

Shin Yokoyama

Publication year - 2001

Publication title -

applied physics letters

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 1.182

H-Index - 442

eISSN - 1077-3118

pISSN - 0003-6951

DOI - 10.1063/1.1420586

Subject(s) - materials science , dielectric , optoelectronics , stack (abstract data type) , capacitor , silicon , gate dielectric , silicon nitride , high κ dielectric , layer (electronics) , semiconductor , oxide , electronic engineering , nanotechnology , electrical engineering , voltage , transistor , computer science , metallurgy , programming language , engineering

We report a high-quality, ultrathin atomic-layer-deposited silicon–nitride/SiO2 stack gate dielectric. p+-polycrystalline silicon gate metal–oxide–semiconductor (MOS) capacitors with the proposed dielectrics showed enhanced reliability with respect to conventional SiO2. An exciting feature of suppressed soft-breakdown (SBD) events is observed in ramped voltage stressing which has been reconfirmed during time-dependent-dielectric breakdown measurements under constant field stressing. Introducing the idea of injected-carrier-induced localized physical damages resulting in the formation of conductive filaments near both Si/SiO2 and poly-Si/SiO2 interfaces, a model has been proposed to explain the SBD phenomena observed in the conventional SiO2 dielectrics. It is then consistently extended to explain the suppressed SBD in the proposed dielectrics. The reported dielectric can be a good choice to meet the urgent need for highly reliable ultrathin gate dielectrics in nanoscale complementary-MOS technology.

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