HRTEM image simulations of structural defects in gate oxides

In this study, we performed HRTEM image simulations of a MOSFET device to determine the ability of HRTEM to detect gate oxide defects. The gate oxide was modeled as an amorphous silicon oxide 16.3 A-thick, sandwiched between a gate and substrate. Both the gate and substrate were modeled as (100) silicon viewed along the [110] direction. Crystalline silicon defects were embedded in the model gate oxide and simulated images were calculated using a multi-slice approach with varying defect morphology, composition, size and orientation. Simulations predict that defects should be observable for very small specimen thickness ( 40 A), but not for specimen thickness and defect sizes typical of advanced CMOS devices analyzed in routine laboratory electron microscopy.