Open AccessDLL-based 4-phase duty-cycle and phase correction circuit for high frequency clock tree
Author(s) -
Jaewoo Song,
Hee Am Shin,
Soo Won Kim
Publication year - 2016
Publication title -
matec web of conferences
Language(s) - English
Resource type - Journals
eISSN - 2274-7214
pISSN - 2261-236X
DOI - 10.1051/matecconf/20165412005
Subject(s) - clock generator , duty cycle , delay locked loop , clock domain crossing , computer science , synchronous circuit , phase locked loop , electronic engineering , clock signal , jitter , electrical engineering , engineering , voltage