Open AccessAn enhanced single gate driven voltage‐balanced SiC MOSFET stack topology suitable for high‐voltage low‐power applications
Author(s) -
Wang Rui,
Jørgensen Asger Bjørn,
MunkNielsen Stig
Publication year - 2021
Publication title -
iet power electronics
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.637
H-Index - 77
eISSN - 1755-4543
pISSN - 1755-4535
DOI - 10.1049/pel2.12227
Subject(s) - mosfet , topology (electrical circuits) , stack (abstract data type) , snubber , silicon carbide , voltage , electronic engineering , high voltage , electrical engineering , gate driver , power semiconductor device , computer science , power (physics) , materials science , engineering , transistor , capacitor , physics , quantum mechanics , metallurgy , programming language
In the fabrication of some high‐voltage low‐power applications, low cost is much concerned, and thus using silicon carbide (SiC) MOSFET stack consisting of series connected low‐voltage devices is preferred rather than using an expensive single high‐voltage device. Therefore, a cost‐efficient single gate driven voltage‐balanced SiC MOSFET stack topology is proposed in this paper, where only some passive components are equipped with the stack. With a concept of single gate driver, the gate driver design of an SiC MOSFET stack is simplified. With an automatic balancing circuit which operates well with the sequential lagging single gate driver, good voltage balancing of SiC MOSFETs in the stack is realized without causing much extra loss and no additional active control is required. The working principle is illustrated in detail and the parameter selection together with design consideration is presented. Next, this topology is compared with RCD snubber method and active delay adjusting method to better illustrate its advantages. Finally, in a typical high‐voltage low‐power application, auxiliary power supply, the simulation and experimental results further verify the effectiveness of the proposed topology.