Developing static model of fault current limiter technologies | Zendy

Ali Kazerooni | Zendy; Jonathan Berry | Zendy; Georgia Tsigara | Zendy; Neil Murdoch | Zendy

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Developing static model of fault current limiter technologies

Author(s) -

Ali Kazerooni,

Jonathan Berry,

Georgia Tsigara,

Neil Murdoch

Publication year - 2017

Publication title -

cired - open access proceedings journal

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 0.23

H-Index - 13

ISSN - 2515-0855

DOI - 10.1049/oap-cired.2017.0932

Subject(s) - limiter , fault current limiter , transient (computer programming) , resistive touchscreen , fault (geology) , electrical impedance , core (optical fiber) , power (physics) , computer science , network analysis , transient analysis , electronic engineering , electrical engineering , reliability engineering , engineering , electric power system , transient response , physics , telecommunications , seismology , geology , quantum mechanics , operating system

Fault Current Limiter (FCL) devices usually have a nonlinear and complex transient behaviour during a fault. Standard desktop short-circuit studies carried out by network operators is static analysis (rather than dynamic analysis) which includes calculations of fault levels at peak Making time and Breaking time. In this paper, a methodology for including FCLs in standard short-circuit studies is proposed. The impedance of FCLs obtained from the manufacturers is presented and used to develop computer models for two Resistive Superconducting and Pre-Saturated Core FCLs. This paper is based on learning to date from Western Power Distribution’s (WPD) Tier-2 Low Carbon Networks (LCN) Fund project, FlexDGrid.

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