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Fault Current Limiter (FCL) devices usually have a nonlinear and complex transient behaviour during a fault. Standard desktop short-circuit studies carried out by network operators is static analysis (rather than dynamic analysis) which includes calculations of fault levels at peak Making time and Breaking time. In this paper, a methodology for including FCLs in standard short-circuit studies is proposed. The impedance of FCLs obtained from the manufacturers is presented and used to develop computer models for two Resistive Superconducting and Pre-Saturated Core FCLs. This paper is based on learning to date from Western Power Distribution’s (WPD) Tier-2 Low Carbon Networks (LCN) Fund project, FlexDGrid.

Developing static model of fault current limiter technologies