Diminished-1 modulo 2n+1 squarer design
Author(s) -
H.T. Vergos,
C. Efstathiou
Publication year - 2005
Publication title -
iee proceedings - computers and digital techniques
Language(s) - Uncategorized
Resource type - Journals
eISSN - 1359-7027
pISSN - 1350-2387
DOI - 10.1049/ip-cdt:20055037
Subject(s) - modulo , adder , arithmetic , modulo operation , residue number system , cryptography , computer science , moduli , mathematics , algorithm , discrete mathematics , telecommunications , physics , quantum mechanics , latency (audio)
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