Simultaneous routing and buffering in SOC floorplan design | Zendy

Jiawei Fang | Zendy; Yang-Shan Tong | Zendy; SaoJie Chen | Zendy

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Simultaneous routing and buffering in SOC floorplan design

Author(s) -

Jiawei Fang,

Yang-Shan Tong,

SaoJie Chen

Publication year - 2004

Publication title -

iee proceedings - computers and digital techniques

Language(s) - English

Resource type - Journals

eISSN - 1359-7027

pISSN - 1350-2387

DOI - 10.1049/ip-cdt:20040072

Subject(s) - floorplan , routing (electronic design automation) , computer science , placement , parallel computing , integrated circuit layout , scheme (mathematics) , embedded system , physical design , integrated circuit , circuit design , mathematics , operating system , mathematical analysis

An EDA tool to deal with the problems of routing and buffer-insertion in system-on-chip floorplanning simultaneously is developed. This routing and buffering tool mainly consists of a Manhattan routing (MR) algorithm and a maze-based between-buffer routing algorithm. Since the processing speed of its MR is very fast, this tool can be integrated into an iterative floorplanning algorithm to promote the routability of a floorplan solution.

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