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Automatic router for the pin grid array package
Author(s) -
S. -S. Chen,
J. -J. Chen,
ChiaChun Tsai,
SaoJie Chen
Publication year - 1999
Publication title -
iee proceedings - computers and digital techniques
Language(s) - English
Resource type - Journals
eISSN - 1359-7027
pISSN - 1350-2387
DOI - 10.1049/ip-cdt:19990797
Subject(s) - router , interconnection , routing (electronic design automation) , very large scale integration , computer science , core router , one armed router , planar , grid , routing table , layer (electronics) , chip , embedded system , parallel computing , computer hardware , computer network , materials science , routing protocol , operating system , nanotechnology , telecommunications , mathematics , geometry

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