Effects of technology mapping on fault-detection coverage in reprogrammable FPGAs | Zendy

Kevin Kwiat | Zendy; W.H. Debany | Zendy; Salim Hariri | Zendy

AI Assistant Blog Pricing

Home ZAIA Blog

Open Access

Effects of technology mapping on fault-detection coverage in reprogrammable FPGAs

Author(s) -

Kevin Kwiat,

W.H. Debany,

Salim Hariri

Publication year - 1995

Publication title -

iee proceedings - computers and digital techniques

Language(s) - English

Resource type - Journals

eISSN - 1359-7027

pISSN - 1350-2387

DOI - 10.1049/ip-cdt:19952234

Subject(s) - field programmable gate array , computer science , programmable logic array , fault (geology) , field (mathematics) , complex programmable logic device , embedded system , logic block , automatic test pattern generation , programmable logic device , logic gate , computer engineering , computer hardware , parallel computing , computer architecture , algorithm , engineering , electronic circuit , mathematics , electrical engineering , seismology , pure mathematics , geology

Although Field-Programmable Gate Arrays (FPGAs) are tested by their manufacturers prior toshipment, they are still susceptible to failures in the field. In this paper, test vectors generated forthe emulated (i.e., mission) circuit are fault simulated on two different models: the original viewof the circuit, and the design as it is mapped to the FPGA's logic cells. Faults in the cells and inthe programming logic are considered. Experiments show that this commonly-used approach failsto...

The content you want is available to Zendy users.

Already have an account? Click here to sign in.

Having issues? You can contact us here

Accelerating Research