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VLSI design of clustering analyser using systolic arrays
Author(s) -
M.F. Lai,
Michio Nakano,
Yebo Wu,
ChaurHeh Hsieh
Publication year - 1995
Publication title -
iee proceedings - computers and digital techniques
Language(s) - English
Resource type - Journals
eISSN - 1359-7027
pISSN - 1350-2387
DOI - 10.1049/ip-cdt:19951790
Subject(s) - very large scale integration , computer science , cluster analysis , analyser , architecture , parallel computing , systolic array , computer architecture , computer hardware , embedded system , artificial intelligence , visual arts , art , chemistry , chromatography

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