0.7 V Manchester carry look-ahead circuit using PD SOI CMOS asymmetrical dynamic threshold pass transistor techniques suitable for low-voltage CMOS VLSI systems | Zendy

T.-Y. Chiang | Zendy; J.B. Kuo | Zendy

Open Access

0.7 V Manchester carry look-ahead circuit using PD SOI CMOS asymmetrical dynamic threshold pass transistor techniques suitable for low-voltage CMOS VLSI systems

Author(s) -

T.-Y. Chiang,

J.B. Kuo

Publication year - 2005

Publication title -

iee proceedings - circuits devices and systems

Language(s) - English

Resource type - Journals

eISSN - 1359-7000

pISSN - 1350-2409

DOI - 10.1049/ip-cds:20041138

Subject(s) - cmos , very large scale integration , carry (investment) , silicon on insulator , transistor , threshold voltage , electrical engineering , electronic engineering , propagation delay , pass transistor logic , computer science , engineering , voltage , materials science , optoelectronics , finance , silicon , economics

The authors report a 0.7 V Manchester carry look-ahead circuit using partially depleted (PD) SOI CMOS dynamic threshold (DTMOS) techniques for low-voltage CMOS VLSI systems. Using an asymmetrical dynamic threshold pass-transistor technique with the PD-SOI DTMOS dynamic logic circuit, this 0.7 V PD-SOI DTMOS Manchester carry look-ahead circuit has an improvement of 30% in propagation delay time compared to the conventional Manchester carry look-ahead circuit based on two-dimensional device simulation MEDICI results.

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