Low-voltage CMOS four-quadrant multiplier based on square-difference identity

A low-voltage CMOS four-quadrant multiplier based on the square-difference identity ([a+b]/sup 2/-a/sup 2/-b/sup 2/) is presented. This circuit has been implemented in a 0.8 /spl mu/m single-poly double-metal n-well CMOS process. Experimental results show that for a power supply of /spl plusmn/1.5 V, the linear input range of this multiplier is within /spl plusmn/0.5 V with the linearity error less than 1%. The total harmonic distortion is less than 1% with input range up to /spl plusmn/0.5 V. The -3 dB bandwidth of this multiplier is measured to be about 1 MHz. Moreover, it can operate satisfactorily regardless of the transistor body connection. This circuit is expected to be useful in low-voltage analogue signal-processing applications.