Data-reuse exploration under an on-chip memory constraint for low-power FPGA-based systems | Zendy

Qiang Liu | Zendy; George A. Constantinides | Zendy; K. Masselos | Zendy; Peter Y. K. Cheung | Zendy

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Data-reuse exploration under an on-chip memory constraint for low-power FPGA-based systems

Author(s) -

Qiang Liu,

George A. Constantinides,

K. Masselos,

Peter Y. K. Cheung

Publication year - 2009

Publication title -

iet computers and digital techniques

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 0.219

H-Index - 46

eISSN - 1751-861X

pISSN - 1751-8601

DOI - 10.1049/iet-cdt.2008.0039

Subject(s) - computer science , benchmark (surveying) , design space exploration , reuse , field programmable gate array , system on a chip , embedded system , chip , computer engineering , parallel computing , engineering , telecommunications , geodesy , geography , waste management

Contemporary FPGA-based reconfigurable systems have been widely used to implement data-dominated applications. In these applications, data transfer and storage consume a large proportion of the system energy. Exploiting data-reuse can introduce significant power savings, but also introduces the extra requirement for on-chip memory. To aid data-reuse design exploration early during the design cycle...

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