CMOS low dropout regulator with dynamic zero compensation | Zendy

ChiaLi Chen | Zendy; WeiJen Huang | Zendy; Shiqiang Liu | Zendy

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CMOS low dropout regulator with dynamic zero compensation

Author(s) -

ChiaLi Chen,

WeiJen Huang,

Shiqiang Liu

Publication year - 2007

Publication title -

electronics letters

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 0.375

H-Index - 146

eISSN - 1350-911X

pISSN - 0013-5194

DOI - 10.1049/el:20071063

Subject(s) - regulator , low dropout regulator , cmos , compensation (psychology) , dropout (neural networks) , zero (linguistics) , control theory (sociology) , dropout voltage , frequency compensation , electronic engineering , voltage regulator , computer science , engineering , electrical engineering , voltage , control (management) , artificial intelligence , psychology , psychoanalysis , chemistry , biochemistry , gene , philosophy , amplifier , linguistics , machine learning

The output capacitor and its equivalent series resistance (ESR) often limit the stability of a conventional low dropout regulator (LDR). A CMOS LDR with dynamic zero compensation is presented to tolerate the wide range of the output capacitor and the ESR. The stability constraints for the output capacitor with the ESR are derived. The measured LDR is stable for the output capacitor 2nF-47uF with ESR of 0.1-50Omega. The maximum quiescent current of this LDR with a bandgap reference is 43.2uA and its maximum output current is 150 mA for the output voltage of 1.8V.

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