Open Access5V, 8 bit, 100MS/s fully differential CMOS sample-and-hold amplifier
Author(s) -
YuChang Chen,
HenWai Tsao
Publication year - 1996
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
eISSN - 1350-911X
pISSN - 0013-5194
DOI - 10.1049/el:19960234
Subject(s) - sample and hold , fully differential amplifier , amplifier , cmos , differential amplifier , stability (learning theory) , electronic engineering , bit (key) , sample (material) , differential (mechanical device) , direct coupled amplifier , operational amplifier , computer science , current feedback operational amplifier , control theory (sociology) , electrical engineering , engineering , physics , electronic circuit , artificial intelligence , computer security , machine learning , thermodynamics , control (management) , aerospace engineering
A 5 V, 100 MS/s fully differential CMOS sample-and-hold amplifier (SHA) with 8 bit accuracy is proposed. Based on the stability limitations of closed-loop SHAs studied in a previous paper (see Int. J. Electron., vol. 78, no. 5, p. 907-910, 1995), the proposed SHA is implemented by an open-loop structure using the 'gain-enhanced unity-gain amplifier' to avoid the stability problem and achieve highe...
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