Open AccessCMOS four-quadrant multiplier using triode transistors based on regulated cascode structure
Author(s) -
Tsay,
ChienHao Liu,
JiannJong Chen,
Jiezhong Wu
Publication year - 1995
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
eISSN - 1350-911X
pISSN - 0013-5194
DOI - 10.1049/el:19950638
Subject(s) - triode , total harmonic distortion , cmos , cascode , transistor , electrical engineering , transconductance , voltage , pmos logic , multiplier (economics) , electronic engineering , optoelectronics , materials science , engineering , resistor , economics , macroeconomics
A new CMOS four-quadrant multiplier consisting of two MOS transistors operated in the triode region with regulated cascode structures is introduced. This circuit employs the essential property that MOS transistors are bi-directional (or symmetric) devices. Simulation results show that for supply voltages of ±3 V, this circuit has <1% linearity error for a differential input range up to ±1.8 V. Total harmonic distortion (THD) with a 1.8 V (peak) input signal at either input terminal with a ±1.8 V DC voltage at the other terminal is less than 1%. The simulated -3dB bandwidth of this multiplier is -17 MHz
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