Open AccessA novel buffering fault‐tolerance approach for network on chip (NoC)
Author(s) -
Jafarzadeh Nima,
Jalili Ahmad,
Alzubi Jafar A.,
Rezaee Khosro,
Liu Yang,
Gheisari Mehdi,
Sadeghi Bigham Bahram,
Javadpour Amir
Publication year - 2023
Publication title -
iet circuits, devices and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.251
H-Index - 49
eISSN - 1751-8598
pISSN - 1751-858X
DOI - 10.1049/cds2.12127
Subject(s) - router , fault tolerance , network on a chip , computer science , overhead (engineering) , embedded system , key (lock) , error detection and correction , chip , reliability engineering , computer network , distributed computing , engineering , operating system , telecommunications , algorithm
Network‐on‐Chip (NoC) is a key component in chip multiprocessors (CMPs) as it supports communication between many cores. NoC is a network‐based communication subsystem on an integrated circuit, most typically between modules in a system on a chip (SoC). Designing a reliable NoC against failures that can prevent failure using some measures or preventing error or system failure while failure happens and proper performance became a significant concern. For a reliable design against failures, first, the system should be analysed to discover the critical points. Hence, in this research, it is tried first to investigate the scale of fault tolerance effect on the mechanism in the router on the network by injecting simulated errors, and then these errors are prevented. As the major novelty, the authors implemented a router on a synchronised network and calculated the network buffering fault tolerance by injecting error in the buffer. Specifically, a new method for improving fault tolerance is proposed, which uses the existing resources efficiently. So, it does not impose any overhead on hardware and improves the error tolerance scale. The authors also evaluate it from different perspectives to show its superior performance.