Gate-Tunable Tunneling Transistor Based on a Thin Black Phosphorus–SnSe2 Heterostructure

Tunneling field-effect transistors (TFETs) are of considerable interest owing to their capability of low-power operation. Here, we demonstrate a novel type of TFET which is composed of a thin black phosphorus-tin diselenide (BP-SnSe 2 ) heterostructure. This combination of 2D semiconductor thin sheets enables device operation either as an Esaki diode featuring negative differential resistance (NDR) in the negative gate voltage regime or as a backward diode in the positive gate bias regime. Such tuning possibility is imparted by the fact that only the carrier concentration in the BP component can be effectively modulated by electrostatic gating, while the relatively high carrier concentration in the SnSe 2 sheet renders it insensitive against gating. Scanning photocurrent microscopy maps indicate the presence of a staggered (type II) band alignment at the heterojunction. The temperature-dependent NDR behavior of the devices is explainable by an additional series resistance contribution from the individual BP and SnSe 2 sheets connected in series. Moreover, the backward rectification behavior can be consistently described by the thermionic emission theory, pointing toward the gating-induced formation of a potential barrier at the heterojunction. It furthermore turned out that for effective Esaki diode operation, care has to be taken to avoid the formation of positive charges trapped in the alumina passivation layer.