New Strategies for Engineering Tensile Strained Si Layers for Novel n-Type MOSFET

We report a novel approach for engineering tensely strained Si layers on a relaxed silicon germanium on insulator (SGOI) film using a combination of condensation, annealing, and epitaxy in conditions specifically chosen from elastic simulations. The study shows the remarkable role of the SiO 2 buried oxide layer (BOX) on the elastic behavior of the system. We show that tensely strained Si can be engineered by using alternatively rigidity (at low temperature) and viscoelasticity (at high temperature) of the SiO 2 substrate. In these conditions, we get a Si strained layer perfectly flat and free of defects on top of relaxed Si 1- x Ge x . We found very specific annealing conditions to relax SGOI while keeping a homogeneous Ge concentration and an excellent thickness uniformity resulting from the viscoelasticity of SiO 2 at this temperature, which would allow layer-by-layer matter redistribution. Remarkably, the Si layer epitaxially grown on relaxed SGOI remains fully strained with -0.85% tensile strain. The absence of strain sharing (between Si 1- x Ge x and Si) is explained by the rigidity of the Si 1- x Ge x /BOX interface at low temperature. Elastic simulations of the real system show that, because of the very specific elastic characteristics of SiO 2 , there are unique experimental conditions that both relax Si 1- x Ge x and keep Si strained. Various epitaxial processes could be revisited in light of these new results. The generic and simple process implemented here meets all the requirements of the microelectronics industry and should be rapidly integrated in the fabrication lines of large multifinger 2.5 V n-type MOSFET on SOI used for RF-switch applications and for many other applications.