On the Mechanical Stresses of Cu Through-Silicon Via (TSV) Samples Fabricated by SK Hynix vs. SEMATECH – Enabling Robust and Reliable 3-D Interconnect/Integrated Circuit (IC) Technology

One of the key enablers for the successful integration of 3-D interconnects using the Through-Silicon Via (TSV) schemes is the control of the mechanical stresses in the Cu TSV itself as well as in the surrounding silicon substrate. The synchrotron-sourced X-ray microdiffraction technique has been recognized to allow some important advantages compared to other techniques in characterization of the mechanical stresses in a TSV sample. This approach have been used to study Cu TSV samples from SK Hynix, Inc. earlier as well as more recently from SEMATECH, and we have found interesting differences in the stress states of the Cu TSV. We proposed a possible explanation of the observed differences. This fundamental understanding could lead to improved stress control and hence reliability in the Cu TSV samples, as well as to reduce its impact to the silicon electron mobility and hence to device performance in general