Column-Parallel Single Slope ADC with Digital Correlated Multiple Sampling for Low Noise CMOS Image Sensors | Zendy

Yue Chen | Zendy; Albert Theuwissen | Zendy; Youngcheol Chae | Zendy

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Column-Parallel Single Slope ADC with Digital Correlated Multiple Sampling for Low Noise CMOS Image Sensors

Author(s) -

Yue Chen,

Albert Theuwissen,

Youngcheol Chae

Publication year - 2011

Publication title -

procedia engineering

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 0.32

H-Index - 74

ISSN - 1877-7058

DOI - 10.1016/j.proeng.2011.12.312

Subject(s) - image sensor , photodiode , correlated double sampling , cmos , fixed pattern noise , column (typography) , noise (video) , sampling (signal processing) , pixel , noise reduction , detector , reduction (mathematics) , electronic engineering , materials science , optics , engineering , physics , computer science , optoelectronics , image (mathematics) , mathematics , artificial intelligence , telecommunications , amplifier , geometry , frame (networking)

This paper presents a low noise CMOS image sensor (CIS) using 10/12 bit configurable column-parallel single slope ADCs (SS-ADCs) and digital correlated multiple sampling (CMS). The sensor used is a conventional 4T active pixel with a pinned-photodiode as photon detector. The test sensor was fabricated in a 0.18 colonm CMOS image sensor process from TSMC. The ADC nonlinearity measurement result shows totally 0.58% nonlinearity. Using the proposed column-parallel SS-ADC with digital CMS technique, 65% random noise reduction is obtained. The significant noise reduction enhances the sensor's SNR with 9 dB

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