Evaluating Performance and Energy-efficiency of a Parallel Signal Correlation Algorithm on Current Multi and Manycore Architectures
Author(s) -
Arne Hendricks,
Thomas Heller,
Andreas Schäfer,
Max Kasparek,
Dietmar Fey
Publication year - 2016
Publication title -
procedia computer science
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.334
H-Index - 76
ISSN - 1877-0509
DOI - 10.1016/j.procs.2016.05.484
Subject(s) - computer science , scalability , cuda , multi core processor , efficient energy use , code (set theory) , parallel computing , computer architecture , embedded system , performance improvement , variety (cybernetics) , signal (programming language) , computer engineering , operating system , artificial intelligence , operations management , set (abstract data type) , electrical engineering , economics , programming language , engineering
Increasing variety and affordability of multi- and many-core embedded architectures can pose both a challenge and opportunity to developers of high performance computing applications. In this paper we present a case study where we develop and evaluate a unified parallel approach to a signal-correlation algorithm, currently in-use in a commercial/industrial locating system. We utilize both HPX C++ and CUDA runtimes to achieve scalable code for current embedded multi- and many-core architectures (NVIDIA Tegra, Intel Broadwell M, Arm Cortex A-15). We also compare our approach onto traditional high-performance hardware as well as a native embedded many-core variant. To increase the accuracy of our performance analysis we introduce dedicated performance model
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