Open AccessFaFNoC: A Fault-tolerant and Bufferless Network-on-chip
Author(s) -
Armin Runge
Publication year - 2015
Publication title -
procedia computer science
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.334
H-Index - 76
ISSN - 1877-0509
DOI - 10.1016/j.procs.2015.07.226
Subject(s) - crossbar switch , computer science , router , fault tolerance , deflection routing , network on a chip , redundancy (engineering) , one armed router , very large scale integration , computer network , architecture , core router , parallel computing , embedded system , distributed computing , routing (electronic design automation) , computer architecture , routing protocol , static routing , operating system , art , telecommunications , visual arts
Deflection routing is a promising approach for energy and hardware efficient NoCs. Future VLSI designs will have an increasing susceptibility to failures and breakdowns. The inherent redundancy of NoCs can be used to tolerate such failures. We extended the non-fault-tolerant CHIPPER router architecture to enable fault-tolerance. This architecture is based on deflection routing and utilizes a permutation network instead of a crossbar. Compared to a crossbar based design, a permutation network allows a faster and smaller router design. Simulations of a 8 × 8 network and more than 30.000 flit injections show, that our router architecture iscompetitive with existing crossbar based fault-tolerant router architectures
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